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URL:https://www.learndesk.us/class/6638605365673984/systemverilog-assertions-and-functional-coverage-from-scratch?ref=outlook-calendar
SUMMARY:SystemVerilog Assertions and Functional Coverage From Scratch
DTSTART;TZID=America/Los_Angeles:20260405T190000
DTEND;TZID=America/Los_Angeles:20260405T200000
LOCATION:https://www.learndesk.us/class/6638605365673984/systemverilog-assertions-and-functional-coverage-from-scratch?ref=outlook-calendar
DESCRIPTION: 
SystemVerilog assertions and functional coverage is a comprehensive from-scratch course on assertions and functional coverage languages that cover features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who has published the second edition of a book on SVA and FC in 2016 and holds 18 U.S. patents in design verification. The course has 50+ lectures and is 12+ hours in length that will take you to step by step through the learning of the languages.
The knowledge gained from this course will help you find and cover those critical and hard to find design bugs. SystemVerilog assertions and functional coverage are very important parts of overall functional verification methodology, and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will be highlights of your resume when seeking a challenging job or project. The course offers a...

https://www.learndesk.us/class/6638605365673984/systemverilog-assertions-and-functional-coverage-from-scratch?ref=outlook-calendar
STATUS:CONFIRMED
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