Hello, and welcome to lecture number seven. In this lecture, we will see why cart beans, ignore beans, illegal Beans, beans off and beans of intersect. What these features really help you with is that when you create a PowerPoint, and when you create hundreds of bins, you need features and facilities so that you can pare down this number of bins that are created into a more manageable set, and more importantly a set that makes more sense to you for their design. So let's look at each one of them individually and see how they work. Let's start with a wild card Bill's wild card as you know from Vera log and system Verilog works exactly the same way as you would use a wildcard in a case statement for example. So let's look at this example here cover group g See at Paul Joseph Clark.

I'm creating a PowerPoint for ADR one. I haven't shown the declaration of ADR one, but it's a four bit wide address bus. Now what I'm doing is I want to create some bins for this for big fight ad are one. But there are, there's a lot of redundancy or a lot of reputation in my specifying of this base. So I'm going to create a wildcard base wildcard is a keyword. So I'm going to say wildcard bands, Inc, name of the bins.

And I'm simply going to say that go over all the four different values of address one as specified with one one question mark, question mark. What that means is the address one can have value 110011011110 and 11111. Any of these four values is hit, then this beans aim should be considered covered. Similarly, what I've done here is again, because of the brackets, the simulator is going to auto generate all the required beans to meet the requirements on the right hand side and the right hand side is a transition veins. So I'm simply going to say, to take big to take B zero x zero x transitions to take B one x where x is a wild card, just like question mark is a wildcard and also z can be a wildcard. So this means there are four transitions that I want to cover 0002100021101210 and 01211 which is rather obvious.

So this basically helps you with you know repetitious typing and the very easy to code your Complex transitions or your complex values. And similarly, this is similar to the previous line only that I am re emphasizing the fact that if you do not have this brackets, then there is only one Bains that is created for all four transitions, when you have this bracket for bins are created for for transitions, for bins for for transitions mean that each of the transition needs to be covered separately and then the particular bin associated with that transition is considered covered. While in this case, there's only one Bains so anytime any of the four transition, let's say your test bench exercise is only one of the four transitions then this bench will be considered covered. It won't wait for all the four transitions to take place. So you need to be careful when you use the auto generated beans.

Works is when you don't. And here's a simulation log, which which shows all the different things that are created. Here's is the one being a bank as shown here. Then here there are four bins, because of these brackets, which are shown here 1234. And here again one been for the ad RB two is created, which is shown here, and everything is covered in this particular example. So as you can see, wildcard beans can be very useful in specifying complex transitions or values without typing each of the required value or transition.

Now let's ignore base. So again, as I said at the beginning of the lecture, you make create a lot of bins. A core point let's say for example, a 32 bit bus is to raise to 32 bins, and you must have a way to say okay out of this to raise to 30 to ignore certain bins minute ignore certain values. So let's see this example. What I've done here is, here's the idea one four bit address bus. I have a covered group at pauses of clock.

And I'm creating a PowerPoint for this variable ad r1. Inside this PowerPoint I'm going to create, I'm going to ignore some bins. What does what does that mean? Ignore underscore bins is the key word. Here is the name of the ignorance. And what I'm saying is that whenever the value of add one is four, or five, then ignore the coverage for those.

That means if my test bench never exercises the value four or five, that's okay, because I don't care. I'm going to ignore it. Similarly, the next line says he ignore everything from six till the end of this particular address range, which is six to 15 in our case, because this one is a four bit wide bus. So this is this is a way you can say okay, out of total 16 values of ADR one, ignore everything from four to 15. And I only care that my test bench exercises the value 012 and three. So that's what is shown here in the simulation log where the first ignore balance and the second ignore balance have both a zero reserve that means we never exercised those and that's okay.

The simulation log won't tell you that is not covered. It is not covered or is it covered, we don't care. And then there are four veins remaining because we're ignoring four to 15. So 0123 is left and all the 16 beans are auto generated. So we are ignoring photo 15 and 012. And three, we need to cover value values of ad r1 being zero or one or two or three needs to be covered.

And that's what we have covered here. And that's what the simulation law shows. So that is ignore bits. Similarly illegal bits, this is very interesting. This is very interesting. For example, what what this really is trying to say is, if your testament ever creates a certain value, then that's a problem.

You For example, if your testament tries to write or reserve bait, then that makes no sense. So what we are basically trying to do here is any values that you do not want to create. And if you ever see those values in during simulation, you want to consider them illegal and you want To see an error. So here's Mike our group GC pauses of growth. And my PowerPoint for the same address variables that I've been using in many examples. What I'm saying in this counterpoint ADR one is number one, I'm not generating any bins.

So that's what I'm saying here. The first note that says no beans is specified as to be system Verilog will create one order bean for each of the 16 address one base, that means there will be 16 Auto beans automatically generated beans that will be created by the simulator. What I'm also saying is that illegal bins, which is the key word, whenever the value of ADR one is zero, then issue an error. I should never drive address one equal to zero from my test page. And here's the actual error that I get from the simulation lab. Where it clearly says that illegal range been value zero got covered that means you did drive zero, but you should not have given zero.

And as I said, there are 16 Auto bins generated. So, in the log you will see zero to 15. And since we did driver zero illegal means I will do zero it says it occurred and then you will get this error. So, these this innovate is a check on your test bench itself. Because sometimes attachments may drive certain values that may cause certain bugs in the design. And after a long iterative loop of debug, someone will come to the conclusion that the test was wrong.

You can never drive certain certain values. Otherwise the design is not specified design does not know what It will do. And some people consider these as negative verification, which is actually very important. And it's also something you should keep in mind. But there are times when you simply cannot issue certain values, and that's where this feature comes into picture. Now, this is very interesting.

This is another way of what I said earlier, paring down the number of beans that you can write. Okay, let's see. This is an interesting example. Same old cover group GCF pauses of clock. What I'm doing is I'm creating a core point for B B's a four big bus. Inside, discovering I'm creating two bins, one bins to cover the values from zero to 12 value of b from zero to zero and the second wind cc To call the values from 13 to 16 of the variable b.

So this is straightforward, then what I'm doing is I'm creating a cross I'm creating a cross with the variable two bit wide variable a with the Tobin's not that that there are only two ways again there is no bracket here. So cross a with two bins off BC. So, you will there so four into two you get eight different bins from this cross which are here a zero BB a one BB a BB and a three BB BB being the one of the bins of BC and a being the value of the variable a and similarly, a zero to a three three cross Vcc so two bins of BC cross with He will give you eight bits. Now give this in your back pocket has been see how this can be further pared down. So let's say you do a cross or too large color points, and you get a hundreds of bins.

But out of those hundreds of bins, you're only interested in certain bends you need to intersect those with certain values for example, so that's where this comes into picture. Inside this cross, remember these squiggly brackets are associated with this cross. So what it means is of all the cross products that are generated here, do the following. So first thing we do is we set bins give it a name, I set a B, and then we are saying this bin will contain only bins off VC bins off is a key word. bins of BC how many beans to be having BC to baby and CC and intersect these beings of BC with value zero and one. That means pick only those beans or BC how many beans were there of BC eight like we just saw.

Only pick those beans of this eight bins which intersect with the value zero and one. If you notice in this VC bins BB is the only one that has the value zero or one, not CC. So out of eight bins Cross of ABC eight bins we only want to pick those bins which interests intersect with value zero or one. And hence since cc has does not have the value zero or one, we are going to pick only for a zero to a three cross with BB as a products that must be satisfied to cover this bits isec a b Maybe a little. There is some detail here that you need to understand. But it's, it's very straightforward once you get the point.

And in this line, all I'm doing is I'm simply negating what I did in the previous line. But what I'm saying here is take bins of BC. Again bins of BC are these two bins BB and CC intersect these beans with values zero to three and zero to three value only occurs in the bins BB and take an intersect of this two if you ignore the bang sign for a moment. That means a VC intersecting with values zero to three will give you exactly the same number of bins that we got in the previous line. But because there is a knot here, we are going to ignore these four bins and we're only going to pick the cross Vcc from all the eight cross products that we had. So, studied this slide frequently and and and you will get the point.

And this will be very useful because my examples are very small, my variables are only four bits wide and so on and so forth. But in the real life, you will have hundreds of bins that will be generated either automatically or you will generate it yourself. And you must have a way of batting down and to those bins that makes more sense to you for your design. So, that's where this will come into the picture. So, that's all folks. These are just four different features that I wanted to introduce to you.

Again, these features will help you pare down or narrow down the number of beans that you generate. Thank you for attending the lecture and I'll see you in the next lecture soon.