Hello and welcome to lecture five. In this lecture, we will go through the clocking basics of concurrent assertions in in a simulator like system Verilog every time tech is divided into different regions and everything gets executed within these regions and then the simulation Time goes to the next simulation time tick. Now, if you have noticed since the system Verilog assertions, syntax and semantics are completely orthogonal to system Verilog there is hardly any relationship between the two. So, why have one language with two completely different syntax and semantics? Well, one of the main reason is that you can have a single language environment for your project you don't have to maintain two different languages So in order to have a single language environment, the system or log assertions, semantics has race condition avoidance built in. And concurrency semantics are built into the language.

Okay with that Prelude, let me show you the different regions that are actually more regions than what I've shown here. But I'm only concentrating on the ones that are important to us in the system or local assertions. If you have pre bond region and this is probably the most important region for us, for simulation, you have active inactive and non blocking assignment regions, then you have the observed region, the active region, and finally the postponed region. prepon region means that the value at this simulation time value of variable let's say is coming easy. A value that existed in the previous time slot and this is very important, as you will soon see, what that means is that as I just say the value that you see in this time take is from the pre bond region. The most one of the most important concepts that you need to understand in sitaula Sessions is that everything whenever I say simply sampling edge or clock edge that we have seen so far, the value of the signal at that particular edge is the value of the signal that existed in the preborn region of the simulation time take that means is the previous value.

For example, let's say at this pause of clock, you have a variable called a let's say a goes hi From zero to one, the same time that the clock goes high. So if you look into the waveform you'll say hey is one red bar bar at the bottom of clock. But for assertions, the value of a deposit of clock will be zero. And the let's say if you say a implies whatever, then A is not one at the edge of love clock is zero, even if a stays one until the next clock, then it will be one of the next pauses of clock. But again, at this pauses of clock, if a also goes high at exactly the same time at the passage of clock, the value of A in the prepon region is zero. And it's that value zero value will be considered sampled at This bothers your clock.

So that's why I said in the previous lecture that I will use the word sampled. Because if I say detect then is hired pauses of clock, but if I say sample sampling is always in the pre pawned region, and it will be the value of a at that pauses of clock will be zero. And I will point this out again and again throughout the remainder of the course. Because if you don't understand this, if you're looking at the waveform, you say, hey, why didn't the assertion fire? Or why did the assertion fail? I can see that a is one a positive clock, but the sample value of a positive clock is zero if it was zero in the pre boundary.

Now the assertions This is sampling This is where all the variables get sampled. When does the assertion get evaluated? It's after the non blocking assertion. assignment is evaluated in the so called observed region is where the assertions are evaluated. And it's in the after they are evaluated, we see after the at the end of the evaluation, we determine if the assertion has passed or failed and we execute the action block. So after the object region in the reactive region, the action blocks are executed.

And then post one region basically takes the time to take to the next time slot. So this is important then as the title says sample value in prepon region. That's about the most important concept we have to take away from this particular slide. Okay, now, we'll go into the clocking basics. Now that we are The standard the sampling takes place in the pawn region. This is the same example we have been saying and to reiterate, in case you missed that in the previous lecture, everything must be sampled at a sampling age, which is pauses of clock in this particular example.

And again see sod rack and grant a sample at the sampling edge even though there is no sampling edge in the sequence it inherited from the property and in case you forget some of the concepts, I have left some notes here you can pause the slide and understand it. Now, another thing I want to point out which I have in some previous lecture is that I keep showing the synchronization pauses of clock or not negative clock. What this can be an asynchronous edge Not an expiration not a level sensitive control, but an asynchronous edge as well. For example, the clock expression can be more complex, you can have clock and then getting signals. So, you can have a gated clock in this particular gated clock as assembling edge in this assertion. Further talking basics, the clock can be defined in a sequence, a dog can be defined in a property which is what we have seen so far and a clock can be defined directly in the assert statement itself.

So, the sampling age can be defined in a sequence a property or in the asserts statement. And the beauty is that this clock a dissembling edge will be inherited to the rest of the assertion. No matter where it's defined from here, we'll go here and then and from here it will go to the sequence as well as the a certain distance that is going to evaluate the property at pauses of clock. My recommendation is that you define the clock in the property. First of all, you can define it in there's nothing wrong with that. But sometimes with the disabled conditions, and other expressions, this becomes a very long statement very cumbersome.

Sequences, I don't recommend putting the clock in sequence, because sequences should be kept quote unquote generic, wide off any sampling edge. They sequences can be reused. They can be reused in a property where which has a different sampling edge than The property in which it was used earlier. Keeping the sampling edge in property is, is really the optimal way to go. Because first of all is very readable if I'm looking at a property. My first reaction is I want to know what's the sampling age.

I don't have to look at the assert statement. I don't want to look at the sequence property, we'll call the sequence. I know what my sampling age is, whatever the property specifies. So that's my suggestion on how you want to or where you want to put the sampling edge. There is also the concept of default clocking clock. So and you define it as default clocking which are the key words before clocking name of the clocking block, cb one, and you say that at balls clog is the default clock for all the properties and sequences that follow.

So default clocking and clocking are keywords, property check requests can will there is no clock here it will take the default property, which basically implies also does not have any clock, it will take the default clock position of clock, and then you can assert the property, so on and so forth. You can also take the default blocking block and embed Gordon code inside the clocking block the properties and then you can set the properties you have to set the properties outside of the clocking block. I do not, personally is just a personal days sort of thing. I highly recommend not to use this, leave the properties outside of the clocking blog, simply define the clocking block, and then use it in properties where you don't have to explicitly define the sampling age. If you look at this diagram, the top diagram, the properties take the default clock.

Now let's say you have 100 different properties, and you're looking at the hundredth property does not have a clock, because it takes a clock from the default clocking block. So you'd have to scroll all the way back up to see what sampling age are we talking about. I tend to not use default clocking blocks, but that's entirely up to you will read papers and publications books very willingly. Default locking block, I personally like to put the sampling edge directly in the property as I said before. So whenever I look at the property I know explicitly right away what the sampling edges but again I'm just pointing this out from my preference you may adopt things differently and in continuing further with the default clocking block, he has a clocking CP one and clocking and module in the module design clocks. And then in the design bus module, more I can do is I can hierarchically refer to this clocking block.

So, top dot design underscore clocks.cb but let's assume that design underscore clocks is also the name of the instance under the bus module. Then you can simply refer to the. So basically with this approach, you can have a module called design talks. All the design blocks for the entire design can be defined in this module. And then in your properties module for example, you can go ahead and use any particular clocking block that you'd like to use as the default clock. Okay, this lecture is very short and simple.

Again, make a note if you're not clear on the pre Pon region sampling values being sampled at the sampling edge, and the value of the sample variable is the value that it had in the pre born region. If you're not clear on that concept, please revisit that and make sure you understand it. Thanks a lot for attending this lecture. I'll see you soon in the next lecture.