Hello and welcome to the system or assertions course. This course is fundamentally a step by step guide to the language, its syntax and semantics methodology. And there will be plenty of applications to solidify your knowledge. We will cover I dribble 1800 2005 subset of the language in its entirety. And we will also include the important features of 2009 and 2012 lRn. This is simply a copyright notice a bit about myself.

My name is Ashok Mehta and I've been working in the industry for over 30 years, mostly in CPU and SOC design and verification. I'm also the author of the book system r assertions and functional coverage. This was published in 2014 by Springer. And in addition, I have 13 us patents in the field of Soc. And lately in 3d, I see design verification. So let's see how will this course benefit you?

First and foremost, the idea behind this course is that it will help you find the critical, elusive, hard to find design bugs, that is the main goal of what you will accomplish by the end of this course. Also note that in today's verification landscape in the industry SVM system or look assertions is a very important part of the overall functional verification methodology. And the verification engineers are required to have this knowledge to be successful. So in verification, As kept you have universal verification methodology, as well as solid assertions and also functional coverage. And the knowledge of SGA will indeed take you further in your career because it will be a highlight of your resume. And note that as I mentioned earlier, there will be plenty of real life applications.

What these applications basically help you do is that you should be able to take those applications and apply to your project in the shortest possible time. The ideal audience is hardware design and verification engineers, verification IP developers, and EDI application engineers and the only knowledge you need is that of the basic knowledge of Verilog and hardware design and verification. You do not need the knowledge of system Verilog object oriented programming or the universal verification methodology. Okay, let's dive a little deeper into water someone logon Sessions is, before we go into further detail of SBA, I want to make sure that we are all on the same page when it comes to SBA under the system or umbrella. So, here's your design under test, you have to generate simulus you have to check the response and then you have to monitor the coverage. In other words, we have to make sure that whatever stimulus that we have provided, has indeed covered both structurally functionally and temporarily, the entire design.

So in system or log 80% of the language is devoted to object oriented programming classes. And in addition, constrained random it is this object oriented programming subset of the language That basically was used to create a universal verification methodology. Then there is another language, which is a subset of system or law or language called functional coverage. And lastly, there is the language system a lot of assertions. What I mean by saying that is a language is that even though it falls into a system or an umbrella, it's completely orthogonal to the system Verilog syntax and semantics. As VA has its own sic syntax and semantics.

The reason it falls under system or umbrella is that the simulation time take synchronizes system Verilog object oriented functional coverage and several other assertions, all three quarter and four languages into one simulation time. So our gist of this course is going to be on system Verilog assertions. One more data point, why is functional verification so important? If you look at this chart, the yellow part is the time and the dollars consumed by verification. And the red is the one consumed by software. If you look at it 80% of the resources of a project, time and dollars are consumed by verification and software.

So basically, functional verification is a long pole to tape up. What can we do to solve this problem? Basically, we need to improve the functional verification productivity, it takes too long, too many iterations, and it's not foolproof. So basically, we need to reduce the time to develop after development, reduce time to simulate and after simulation that you strive to debug, and then go back to this loop. system Verilog assertions helps you reduce time to develop as you will see, as we move forward in the course, it will it also similar as faster than if you had written a behavioral very low counterpart of a system of assertion and, obviously system rollover session pinpoints exactly where the problem is, it will help you tremendously and to complete the story in addition to the verification productivity, we also need to improve the coverage accuracy. So, this is also where SV comes into picture, there is a keyword called cover in SGA and it helps to cover temporal domain logic.

Temporal domain logic cannot be covered either by functional coverage or by structural coverage of code coverage. So, SGA will help in improving the coverage accuracy also in addition to financial coverage and code coverage that you are familiar with system Verilog assertions history, there was a language called sugar from IBM. From there a new language was derived, called properties specification language. There was also a language from Vera called Open Verilog. Open Vera assertions, there was also the spackman II language which had assertions built into it. There was a constraint based verification language from Motorola.

And finally, there was a language called for spec from inter citizen of assertions is a culmination of the technologies developed in each of these languages. It has a comprehensive view of all the pros from each of this language, and that's the benefit of SGA. Okay, folks, this is the end of this lecture, very short lecture. Basically, I wanted to make sure we are on the same page when it comes to a system of assertions is evolution, and how it plugs into the overall system or umbrella. Thank you so much for attending and I'll see you in the next lecture.