Video Part One practical insights into the ESP 32 features. In this video, we will first learn about the various ESP 32 chip variants and the differences later. We will learn in depth the features of the ESP 32 chip. Then we will learn about the internal memory of the ESP 32 chip. And finally, we will learn about the external memory support for the ESP 32 chip. Just like the ESP, a 266 models, ESP 32 chip can also be found in various models with different hardware features.

The datasheet reveals that the ESP 32 chip is manufactured in four different variants. A table comparing the features of the four different chips variants is shown here. The ESP 32 D zero w dq six is a dual core variant. With no embedded flash, it is housed in a quad flat no leads package of size six mm by six mm. This is the initial production release of the chip. The ESP 32 D zero WD is same as the previous package, but housed in a smaller Qf and package of size phi m m by phi mm.

The ESP 32 D two WD is same as the zero WD but has a 16 mega bit of embedded flash clocked at 40 megahertz the ESP 32 s zero wt is same as the zero WD but with only a single core. You can decipher the features of the ESP 32 chip by just looking at its package name. The speaker tells you how to decipher the features. Just by looking at the package name. I will give you an activity to do take your sparkfun ESP 32 thing and try to Read the package identifier. You may need to use a magnifying glass if your eyesight is not good.

Can you tell me what are the features of this package? Sometimes you may come across ESP 32 development boards with a bigger Qf and package. These are called system in package modules which will contain any ESP 32 chip crystal oscillator, flash memory chip filter capacitors and our have matching lens into a single seven mm by seven mm sized Qf n package. ESP 32 Piko default is an example of a CEP many times you will see a metallic enclosure based package on ESP 32 development boards. These are similar to a CEP but these SMD modules can be directly integrated onto other circuit boards, unlike the Qf and packages. Now, let us look at To some practical insights into the features offered by the ESP 32.

The ESP 32 has extensive dual core 32 bit LX six micro processors, they can run at a speed of 600 million instructions per second. The chip will run on breakout boards and modules from 160 megahertz up to 240 megahertz. That is a very good speed for anything that requires a microcontroller with connectivity options. The two cores are named protocol CPU, also known as pro underscore CPU and application CPU, also known as a PP underscore CPU. This basically means that by default, the P zero underscore CPU processor handles the Wi Fi, Bluetooth and other internal peripherals like SPI eye to see ADC etc. The AP underscore CPU is left out for the application code.

This separation of functions is done in the expressive IoT development framework, also known as ESP IDF. The ESP IDF is the official software development framework for the chip, Arduino and other implementations for ESP. 32 development are based on ESP IDF code. The ESP IDF uses free arctos for switching between the processes and data exchange between them. We will implement this in section three using the Arduino ID. An internal memory is provided, which is closely tied to the processes for booting and core functions.

For 48 kilobytes of Read Only Memory is allocated. This is equivalent to the ROM bootloader in personal computers today And instructions. It has 520 kilobytes of on chip SRAM. The internal artists he has a total of 16 kilobytes of RAM, which is divided into two. They are called the artists is slow memory and artists you fast memory. The slow memory can be accessed by the ultra low power core processor in deep sleep mode.

The ump core processor is an independent parameter low power processor used to wake up the main processor from deep sleep mode. Deep Sleep mode is used to reduce power consumption by disabling the main course. The RTC fast memory can be used for data storage, so that the main CPU can access the data saved during deep sleep mode by the UL Pico processor. We will cover deep sleep modes in Section four. The internal memory also consists of one kilobyte of issues of which 256 is used for mac address and chip configuration and the remaining 768 bits are reserved for flash encryption and chip ID. Now, let us look at the external memory support of the ESP 32.

The chip supports up to 416 megabytes of external cue SPI flash, and eight megabytes of external SRAM with hardware encryption. This figure shows the address map of the ESP 32 chip. Note that there is a high speed cache and a memory management unit before the external flash and es gram. Since the processor architecture is 32 bit, the internal peripherals, Wi Fi, Bluetooth, external memories etc, are mapped to two raised to 32 or four GB address space. Also, one interesting thing to notice that both processes are mapped symmetrically to this address space. It basically means a register, for example, can be accessed from the same address location from both the CPUs as shown in this image.

Summary. In this video, we have covered the following topics, comparison of different ESP 32 chip variants in the features of the ESP 32 chip, understanding the internal memory features of the ESP 32 chip, understanding the external memory support and features of the ESP 32 chip. In the next video, we will learn the practical applications of the wireless features listed for the ESP 32