Hello, and welcome to lecture three of this course. In this lecture, we'll discuss immediate assertions. Before we go into the immediate, I just want to point out that in system Verilog assertions, there are three kinds of assertions, immediate, deferred, immediate, and concurrent. Now, concurrent will be discussed pretty much throughout the course, and we'll start discussing it in the next lecture. So in this lecture, we'll concentrate on immediate and deferred immediate. So immediate assertion is simple non temporal domain assertion.

And it basically executes like a statement in a procedural block. So think of it as an expression in the condition of a procedural if statement. It's pretty much like if then else, if else and you're kind of a similar semantic and it can be specified only When a procedural statement is specified, the idea behind this point is that a concurrent assertion can be specified or can be triggered or fired from a procedural block. And most likely you will find it from outside of the procedural block. So keep some of these points in back pocket so that you understand the difference between immediate and concurrent. When we go to the concurrent assertions.

Now, deferred immediate assertions were introduced in IEEE 1800 2009 LRM. If you're still using 2005 LRM, then this assertion will not be available to you. It is an immediate assertion or is a type of an immediate assertion. Now, let me repeat that immediate assertions evaluate immediately without waiting for the variables in his combinatorially expression to settle down. What that means is less Say you hire a equal to B plus C in a Boolean expression. Now, VNC may change from B may go from zero to one to zero and C may go from one to zero to one, the a value will change that many times.

So, every time he changes within the same simulation timetable, the assertion will find either pass or fail. So what this in other words, as you know, in hardware design, we have glitches. So this is basically considered a glitch and the immediate assertion is prone to glitches. In contrast, the default assertion does not evaluate the sequence expression or the Boolean expression until the end of the timestamp, so that again if B goes from 010, c goes from 101. Then the last value of v and C will be looked upon to evaluate a The assertion will fire only once based on the value of a, I will describe the difference between deferred immediate and immediate in a couple of slide with an example. So let's look at an example on how to go the immediate assertion.

In figure in this figure we see that that is an immediate assertion. embedded in procedural block. That is triggered by pause edge of clock. The immediate assertion is triggered after pause edge of beat. So if you if you see the pursuit general blog This is a behavioral blog. At paws edge of dog if a began at paws edge of B, assert B or C, meaning B or C must be true.

When at the passage of D if it is true Then display that the assertion has passed, ELLs, say or US dollar fatal and we'll see what other kinds of system tasks are available here and and and consider it a failure and display a statement as such. So, again, these V or C, that particular expression or Boolean can only be combinational there cannot be any temporal domain sequences. I also want to point out that this else clause in this code applies to this assert and not to this If so, do not make a mistake on that one. The label here is optional, but as you may see, it's very useful. If you don't supply a label, then the simulator will basically apply one with some random number or Get on algorithm. The fatal, as I just said, can be dollar fatal dollar error dollar warning dollar info.

And we'll discuss those things later in the in the chapter. I also want to point out and this is an important point, look at at pauses of D. The assertion fires at an edge sensitive timing control. But it doesn't need to be sensitive, it can be level sensitive also. The reason I'm bringing up this point is that in concurrent assertions, everything will be fine at edge sensitive semantic. You cannot have level sensitive control of a concurrent assertion. So, some of these things, keep those in your back pocket.

When you go to the concurrent assertions you will understand them better. Let's look Get some more example what is it that you need to watch out for? So, if you if Let's look at this example always at positive clock, a bus ack, then we will say assert bus request and and bank reset. If this condition is true, then display that the assertion have passed. If not, then display that it is failed. Now, what some people end up doing is they say hey, after the if the assertion fails, then I want to set the much machine check accepted to binary one because I need to process this particular machine check exception.

But if you do that, basically else you did beginning and this else belongs to this assert, and not to this f just like we saw in the previous slide, but in this begin and if you put days what Cynthia says tools normally They basically ignore the entire sub block. And and so your variable setting also will be ignored, synthesis results will come and you won't know why your code is not working. The other point I want to make is that you cannot use an immediate assertion in a continuous assignment. Bottom line is you cannot use it in a non procedural statement. It has to be inside a procedural statement. Okay, let's, let's go to the deferred immediate assertion.

So let's say let's first look at the immediate assertion. And I was just explaining to you in the example that I quoted a equal to b plus c. Let's say we assign not equal to bank a whenever a is negated that not a set. Now we assert always come begin. we assert Not a means bang, a bang equal to Hey, this is the immediate decision. If you just concentrate on this assertion, then you will see that a may change from zero to one to zero within a given time date, and this assertion may fire multiple times. So there's the concept of deferred immediate assertion comes into picture.

Basically, you put a pound zero in front of the Boolean expression or you put the keyword final in front of the Boolean expression and then this we come to the four different immediate if some of you recall in Verilog also we have a bomb zero which basically delays the action that follows it till the end of the time thing, same thing happens here. So this Boolean will not be evaluated till the end of the 20. And then You will it will not be prone to glitches. Similarly, and this is also a very important feature. We haven't discussed cover yet, but cover basically covers this particular Boolean expression meaning did we exercise this Boolean expression. So, let's say in this example, you have assigned a equal to C or D and B equal to E or D E or F sorry, and in again always calm we say cover B not equal to A.

And he said our bounds zero B naught equal to a and go are final. So, this is the immediate cover, this is the deferred immediate cover and this is also deferred immediate cover. Now, coverage again in immediate A, A, B, C or D and E or F any of these four variables may go transition from zero to one to zero to one for example, and every time the transition takes place, because cover immediate cover is executed immediately this government fired multiple times. Now, the problem with that is it will then in your coverage report give multiple covers of this particular segment even though it needs to be covered only months. So, when you say lb zero and and final to make a deferred immediate cover, then this expression that follows from zero final will be evaluated only once and you will get the true indication of cover whether either is covered or is not covered.

So, this this is important difference between immediate and deferred immediate. I'm going to keep this lecture pretty short. And that's pretty much it to the immediate assertions. Immediate assertions are used by designers, but I'd say that 90 to 95% of the time you're going to use the concurrent assertions. And immediate assertion again, is just like if then else statement in a procedural block. Thanks a lot for attending this lecture, and I'll see you soon in the next lectures.